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Embedded Systems & Robotics Engineering

Bridge software and physical reality. Learn how bits turn into voltage, how memory-mapped registers manipulate silicon, how Real-Time OS kernels prevent race conditions, and how autonomous robots navigate using sensor fusion.

Total Effort:~460 Hours
Pace:40 Weeks (~12h/wk)
Rigor:Systems Intensive
"You Are Here" Progress Tracker
0 of 4 Nodes Mastered
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0% Complete
01
Phase 1Bare-Metal Hardware

Bare-Metal C & Silicon Microcontroller Architecture

Registers, Linker Scripts, Memory-Mapped I/O, and Vector Interrupt Tables on ARM Cortex-M.

1Learner Experience Window
⚡The Wall of Abstraction

What you're experiencing: "Registers & Memory Mapped I/O"

There is no operating system, no stdout, and no safety net. Your program crashed and the microcontroller is in HardFault. You feel blind without a console.

What your internal monologue sounds like right now:
“Where did printf go? How do I even print a number?”
“I flipped a bit in the RCC peripheral clock register and nothing happened — wait, clock gating was disabled!”
“Looking at a datasheet that is 1,200 pages long feels terrifying.”
Neurobiology of this stage

You are stripping away decades of high-level OS abstractions. For the first time, you understand what a CPU really does: fetch, decode, and execute instructions against physical memory addresses.

⚠️ Pitfall to dodge:
  • Forgetting to enable the peripheral clock before accessing register addresses, triggering an immediate BusFault.
  • Not using the `volatile` keyword for hardware registers, leading compiler optimization passes to optimize away hardware poll loops.
Sanity Check & Breakthrough Tactic
Use an inexpensive USB logic analyzer ($10) and PulseView. Seeing the physical square waves on an SPI or UART line makes the invisible visible.
Remember: Discomfort is evidence of synaptic adaptation.Keep coding →
Firmware Fundamentals•Intermediate

Low-Level C: Pointer Arithmetic & Volatile Memory

Struct bitfields, volatile keywords, memory alignment, and casting raw addresses to pointer structs.

⏱️ ~35h•2 Elite Resources
Computer Architecture•Advanced

ARM Cortex-M Architecture & NVIC Interrupt Controller

Startup code, reset handlers, linker scripts, stack pointers (MSP vs PSP), and priority interrupts.

⏱️ ~40h•2 Elite Resources
Capstone Checkpoint⏱️ ~25h Portfolio Spec
Intermediate

Capstone: Bare-Metal UART Driver & Shell from Zero Libraries

Write a complete bare-metal serial boot shell on an STM32 or RP2040 without using vendor HAL or standard C library. Configure PLL clock tree to 72MHz, enable USART transmitter/receiver with circular ring buffer interrupts, and implement interactive commands.

Required Proof-of-Competence Deliverables:
Minimal Linker Script (.ld) and Startup Assembly/C defining vector table
Peripheral register header mapping GPIO and USART registers via memory-mapped structs
Interrupt-driven circular ring buffer for non-blocking serial communication
Command-line interpreter with memory inspect (`peek`/`poke`) functionality
02
Phase 2Real-Time Systems

Real-Time Operating Systems (RTOS) & Concurrency

Preemptive schedulers, semaphores, mutex priority inheritance, and deterministic thread communication.

2Learner Experience Window
💡The Aha! Breakthrough

What you're experiencing: "FreeRTOS & Deadlocks"

Your single `while(1)` super-loop was becoming unmaintainable with delay timers. Moving to RTOS tasks with independent priorities feels like an incredible leap in power.

What your internal monologue sounds like right now:
“I can blink an LED, read an IMU sensor, and listen to a radio packet concurrently without stutter!”
“Why did my high-priority task freeze? Ah, priority inversion because low-priority task held the I2C mutex!”
Neurobiology of this stage

You are mastering deterministic concurrency. You understand that real-time does not mean "fast" — it means guaranteed execution deadlines.

⚠️ Pitfall to dodge:
  • Calling non-ISR-safe FreeRTOS functions inside an Interrupt Service Routine instead of `FromISR` variants.
  • Under-allocating task stack size, leading to silent memory corruption when an interrupt pushes context to the stack.
Sanity Check & Breakthrough Tactic
Always enable stack overflow hooks (`configCHECK_FOR_STACK_OVERFLOW = 2`) during development.
Remember: Discomfort is evidence of synaptic adaptation.Keep coding →
RTOS•Advanced

FreeRTOS Architecture & Task Scheduling

Preemptive priority scheduling, task control blocks (TCB), context switching, and tick timers.

⏱️ ~35h•1 Elite Resources
Capstone Checkpoint⏱️ ~22h Portfolio Spec
Advanced

Capstone: Multi-Sensor Telemetry Logger with FreeRTOS & Queue Routing

Architect an RTOS telemetry logger. A high-priority sensor task samples an accelerometer via SPI at 200Hz, pushes samples to a thread-safe message queue, and a worker task logs records to an SD card with zero missed deadlines.

Required Proof-of-Competence Deliverables:
Producer-consumer architecture with FreeRTOS queues and counting semaphores
Mutex with priority inheritance protecting the shared SPI bus
Watchdog timer task monitoring thread heartbeat
03
Phase 3Robotics & Autonomy

Autonomous Robotics, ROS2 & Sensor Fusion

Robot Operating System 2, URDF kinematic chains, Extended Kalman Filtering, and autonomous navigation.

3Learner Experience Window
🚀Engineering Fluency

What you're experiencing: "ROS2 & Kinematic Control"

You watch a simulated differential-drive robot navigate a virtual room, avoid obstacles, and build an occupancy grid map in RViz. You are designing autonomous machines.

What your internal monologue sounds like right now:
“DDS middleware handles distributed network communication across microcontrollers and companion computers.”
“The robot is actually calculating forward kinematics and generating motor velocities in real time.”
Neurobiology of this stage

You have combined control theory, embedded firmware, distributed networking, and computer vision into an integrated robotic system.

⚠️ Pitfall to dodge:
  • Misaligning coordinate frames in the TF2 transformation tree (e.g. `base_link` vs `odom` vs `map`).
  • Relying purely on wheel odometry without IMU sensor fusion, leading to rapid wheel-slip drift.
Sanity Check & Breakthrough Tactic
Always inspect the TF2 frame tree (`ros2 run tf2_tools view_frames`) whenever a navigation or lidar mapping transform fails.
Remember: Discomfort is evidence of synaptic adaptation.Keep coding →
Robotics Software•Intermediate

ROS2 Architecture: Nodes, Topics, Services & Actions

DDS distributed middleware, publish-subscribe topology, lifecycle nodes, and QoS profiles.

⏱️ ~40h•2 Elite Resources
Capstone Checkpoint⏱️ ~35h Portfolio Spec
Advanced

Capstone: Autonomous SLAM Navigation Robot with ROS2 & Nav2

Build an autonomous differential drive robot in ROS2 simulation (Gazebo). Implement an Extended Kalman Filter (robot_localization) fusing wheel encoders and IMU, generate a 2D occupancy grid with SLAM Toolbox, and autonomous waypoint navigation with Nav2.

Required Proof-of-Competence Deliverables:
URDF robot description with calibrated joints and lidar/camera sensors
EKF configuration fusing IMU and wheel odometry topics
Nav2 costmap parameters and autonomous obstacle avoidance path planning